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<title>Programmable interrupt controller</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Programmable interrupt controller</span></span>

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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC microcontroller</a>.</div>

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<p>In <a href="Computing" title="Computing">computing</a>, a <b>programmable interrupt controller</b> (<b>PIC</b>) is an <a href="Integrated_circuit" title="Integrated circuit">integrated circuit</a> that helps a <a href="Microprocessor" title="Microprocessor">microprocessor</a> (or <a href="CPU" class="mw-redirect" title="CPU">CPU</a>) handle <a href="Interrupt_request_(PC_architecture)" class="mw-redirect" title="Interrupt request (PC architecture)">interrupt requests</a> (IRQs) coming from multiple different sources (like external I/O devices) which may occur simultaneously.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> It helps prioritize IRQs so that the CPU switches execution to the most appropriate <a href="Interrupt_handler" title="Interrupt handler">interrupt handler</a> (ISR) after the PIC assesses the IRQs' relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities. PICs often allow mapping input to outputs in a configurable way. On the <a href="PC_architecture" class="mw-redirect" title="PC architecture">PC architecture</a> PIC are typically embedded into a <a href="Southbridge_(computing)" title="Southbridge (computing)">southbridge chip</a> whose internal architecture is defined by the chipset vendor's standards.

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<div class="mw-heading mw-heading2"><h2 id="Common_features">Common features</h2></div>

<p>PICs typically have a common set of registers: interrupt request register (IRR), in-service register (ISR), and interrupt mask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an <a href="End_of_interrupt" title="End of interrupt">end of interrupt</a> (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.

</p><p>There are a number of common priority schemas in PICs including hard priorities, specific priorities, and rotating priorities.

</p><p>Interrupts may be either <a href="Interrupt#Edge-triggered" title="Interrupt">edge triggered</a> or <a href="Interrupt#Level-triggered" title="Interrupt">level triggered</a>.

</p><p>There are a number of common ways of acknowledging an interrupt has completed when an EOI is issued. These include specifying which interrupt completed, using an implied interrupt which has completed (usually the highest priority pending in the ISR), and treating interrupt acknowledgement as the EOI.

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<div class="mw-heading mw-heading2"><h2 id="Well-known_types">Well-known types</h2></div>

<p>One of the best known PICs, the <a href="Intel_8259" title="Intel 8259">8259A</a>, was included in the <a href="X86_architecture" class="mw-redirect" title="X86 architecture">x86</a> PC. In modern times, this is not included as a separate chip in an x86 PC, but rather as part of the motherboard's <a href="Southbridge_(computing)" title="Southbridge (computing)">southbridge</a> chipset.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In other cases, it has been replaced by the newer <a href="Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">Advanced Programmable Interrupt Controllers</a> which support more interrupt outputs and more flexible priority schemas.

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<ul><li><a href="Intel_8259" title="Intel 8259">Intel 8259</a> – notable PIC from Intel</li>

<li><a href="OpenPIC_and_IBM_MPIC" class="mw-redirect" title="OpenPIC and IBM MPIC">OpenPIC and IBM MPIC</a></li>

<li><a href="Inter-processor_interrupt" title="Inter-processor interrupt">Inter-processor interrupt</a> (IPI)</li>

<li><a href="Interrupt_latency" title="Interrupt latency">Interrupt latency</a></li>

<li><a href="Non-maskable_interrupt" title="Non-maskable interrupt">Non-maskable interrupt</a> (NMI)</li>

<li><a href="IRQL_(Windows)" title="IRQL (Windows)">IRQL (Windows)</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

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</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/content-details/782158/intel-64-and-ia-32-architectures-software-developer-s-manual-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html?wapkw=intel%2064%20and%20ia-32%20architectures%20software%20developer%27s%20manual&docid=782161">"Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A"</a>. <i><a href="Intel" title="Intel">Intel</a></i>. 2023-06-22<span class="reference-accessdate">. Retrieved <span class="nowrap">2025-03-28</span></span>.</cite></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><cite id="CITEREFChristopher_SmallStephen_Manley" class="citation journal cs1">Christopher Small; Stephen Manley. <a rel="nofollow" class="external text" href="https://static.usenix.org/publications/library/proceedings/ana97/full_papers/small/small.html">"A Revisitation of Kernel Synchronization Schemes"</a>.</cite> <span class="cs1-visible-error citation-comment"><code class="cs1-code">{{cite journal}}</code>: </span><span class="cs1-visible-error citation-comment">Cite journal requires <code class="cs1-code">|journal=</code> (help)</span></span>

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<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090203012354/http://www.intel.com:80/Assets/PDF/datasheet/290562.pdf">"82371AB PCI-TO-ISA / IDE Xcelerator (PIIX4)"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="https://www.intel.com/Assets/PDF/datasheet/290562.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2009-02-03.</cite></span>

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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20180408090800/http://www.fullchipdesign.com/tyh/interrupt_controller_vic.htm">Interrupt controller and associated registers.</a></li></ul></div><div><div class="zim-footer">

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